I have been doing image processing related algorithms under System Generator. I feel that SysGen is quite powerful. I have a few whimsy in the past few days. Can I use SysGen to communicate data directly? After all, an HDL code is not written for people who are doing FPGAs. It is very attractive to say.
The serial communication protocol is relatively simple. When transmitting, the 8-bit data is preceded by a 1-bit start bit 0, and after the 8-bit data is added with a stop bit 1, the 8-bit number is expanded into a 10-bit number, and then converted in parallel. It can be sent from GPIO for serial.
The model is built as follows:
Since the model only contains the sending part for the time being, it is not very complicated. In addition, with a button, the data is sent each time the button is pressed.
Select the board model:
Set the clock:
Click Generate to convert to HDL Netlist. This will create a folder under the folder with an ISE project, open it with ISE, and modify the UCF file.
NET "clk" LOC = Y9 | IOSTANDARD=LVCMOS33; # "GCLK"
NET "ce" LOC = P16 | IOSTANDARD=LVCMOS18; # "BTNC"
//NET "rxd" LOC = Y11 | IOSTANDARD=LVCMOS33; # "JA1"
NET "gateway_out[0]" LOC = AA11 | IOSTANDARD=LVCMOS33; # "JA2"
NET "gateway_in[0]" LOC = T18 | IOSTANDARD=LVCMOS18; # "BTNU"
After the integrated wiring generates the bitstream file, download it directly. When you press BTNU, data will be sent. I wrote 0->255 during initialization, and I can see consecutive numbers in the serial port assistant.
At present, only the serial port is sent. After all, this is relatively simple compared to receiving. I haven’t thought about how to receive it. Let me share it with you~~
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