FPGA engineers all know that most of the Verilog code is an always statement, and the structure is basically the same. To reduce repetitive work, let engineers focus on the design and implementation. Mingdeyang elaborates the commonly used templates, as long as you install it. The GVIM provided by Ming Deyang can use these templates.
1. Temporal logic template
Enter "Module" in the GVIM and press Enter, as shown below
You can get the following template for the temporal logic.
The module's template includes input and output signal lists, signal definitions, combinatorial logic, and sequential logic. This is a common module component. The student only needs to understand the meaning of each part and fill in the blanks as required. There is no need to remember it. I see that many students have spent a lot of time to remember and learn the modules when they first started learning. This is meaningless.
2. Enter "Reg" and press Enter.
You can get a single-bit reg signal definition
3. Enter "Reg2" and enter
You can get a 2-bit reg signal definition
4. Enter "Reg8" and press Enter
Can get 8-bit reg signal definition
Similar shortcut commands are:
To use the above shortcut command, you need Mingdeyang's configuration file, welcome to pay attention to Mingdeyang public number "fpga520", or group 97925396. Slogan: Use templates to reduce memory and focus on design.
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