On-chip process variations often lead to severe "clock pessimistic effects" during timing analysis. This problem can be recovered by CPR (Clock Pessimism ReducTIon) operation. However, there are often users who consult us that CPR operation in their design does not reduce the "clock pessimistic effect", but the effect is reversed and does not increase in timing. On the contrary, it is far worse than the timing requirements.
In the setup analysis, CPR is usually added to the target (destination) clock path, thus increasing the required time. However, because the CPR has been removed from the target clock path in the user's design, it takes time to get earlier, rather than delay. The result is that users think they lost time, not compensation time. In fact, the actual situation is that the user has no loss.
When performing OCV analysis, the source path and the target path are considered to have different delay times. However, for the path of the two "shared", the delay time remains the same. CPR compensates for the delay difference, so the value of the delay until the common node becomes the same.
In order to better understand what happened, please check the attached timing analysis report.
(Thanks to Matsuyama-san of Xilinx Tokyo for sharing his timing analysis report for a sample design)
For the sake of simplicity, this report has been modified.
Before MMCME3_ADV_X1Y2, both the source clock and the target clock share a common path, then the source clock goes to the BUFGCE_X1Y48 node, and the target clock goes to the BUFGCE_X1Y50 node.
Let's clarify the delay before the common node (Vivado considers the output of the MMCM to be a common node, although the output pins of the two clock paths are different).
Let's take a look at the source clock path in the timing report:
The starting point of the clock is: 0 (21 lines of the timing report), and the output to the MMCM is -3.218 (31 lines of the timing report). Therefore, the delay before the common node is -3.218.
For the target clock path:
The starting point of the clock is: 3.33 (41 lines of the timing report), and the output to the MMCM is 0.141 (50 lines of the timing report), so the delay of the common node (target clock path) is 0.141-3.33=-3.189.
The latency of the target path (-3.189) appears to be larger than the source clock path delay (-3.218) (note the negative sign, not just the value of the delay).
Therefore, the target path has a higher delay and needs to be compensated. Therefore, the "clock pessimistic effect" is reduced in the target clock, so that the required time can be reduced.
Now, the source clock and the target clock have the same delay before the common node, which means that the user has no loss or extra gain before the common node (such as the MMCM node in the example).
This opposite effect is present in MMCM nodes, which is more prevalent in the 7 series devices than in the UltraScale family of devices.
Attachment link:
Https://forums.xilinx.com/xlnx/attachments/xlnx/tech_blog/4/1/TIming_CPR...
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