The earlier the signal integrity (SI) problem is resolved, the higher the efficiency of the design, thereby avoiding adding termination devices after the board design is complete. SI design planning ...
The earlier the signal integrity (SI) problem is resolved, the higher the efficiency of the design, thereby avoiding adding termination devices after the board design is complete. There are many tools and resources for SI design planning. This article explores the core issues of signal integrity and several methods for solving SI problems, and ignores the technical details of the design process here.
1 The issue of SI With the increase in the speed of IC output switching, regardless of the signal period, almost all designs have encountered signal integrity problems. Even if you have not encountered SI problems in the past, as the operating frequency of the circuit increases, you will definitely encounter signal integrity problems in the future.
Signal integrity issues mainly refer to signal overshoot and damped oscillation phenomena, which are mainly a function of IC drive amplitude and transition time. In other words, even if the wiring topology has not changed, as long as the chip speed becomes fast enough, the existing design will be in a critical state or stop working. We use two examples to illustrate that signal integrity design is inevitable.
In the field of communications, leading-edge telecommunications companies are producing high-speed circuit boards (above 500 MHz) for voice and data exchange. Cost is not particularly important at this time, so multi-layer boards can be used as much as possible. Such a circuit board can be fully grounded and easily form a power circuit, or a large number of discrete termination devices can be used as needed, but the design must be correct and cannot be in a critical state.
SI and EMC experts must perform simulation and calculation before wiring. Then, the circuit board design can follow a series of very strict design rules. In doubt, you can add termination devices to obtain as much SI safety margin as possible. the amount. In the actual working process of the circuit board, there will always be some problems. For this reason, SI problems can be avoided by using controllable impedance terminal wiring. In short, beyond the standard design can solve the SI problem.
The following describes the general SI design guidelines for the design process.
2 Preparations before design Before design starts, you must first think about and determine the design strategy, so as to guide the work such as component selection, process selection and circuit board production cost control. As far as SI is concerned, it is necessary to conduct research in advance to form planning or design criteria to ensure that there are no obvious SI problems, crosstalk or timing problems in the design results. Some design guidelines can be provided by IC manufacturers. However, the guidelines provided by chip suppliers (or guidelines designed by you) have certain limitations. According to such guidelines, it may not be possible to design a circuit board that meets the requirements of SI. If the design rules are easy, there is no need for design engineers.
Before the actual wiring, we must first solve the following problems. In most cases, these problems will affect the circuit board you are designing (or are considering designing). If the number of circuit boards is large, this work is valuable.
3 Lamination of circuit boards Some project groups have great autonomy in determining the number of PCB layers, while other project groups do not have this autonomy, so it is important to know where you are. Communicating with manufacturing and cost analysis engineers can determine the stacking error of the circuit board, and it is still a good opportunity to find circuit board manufacturing tolerances. For example, if you specify a layer with 50Ω impedance control, how does the manufacturer measure and ensure this value?
Other important questions include: What are the expected manufacturing tolerances? What is the expected insulation constant on the circuit board? What are the tolerances for line width and spacing? What are the tolerances for the thickness and spacing of the ground and signal layers? All this information can be used during the pre-wiring phase.
Based on the above data, you can choose to cascade. Note that almost every PCB inserted into another circuit board or backplane has a thickness requirement, and most circuit board manufacturers have fixed thickness requirements for the different types of layers that they can manufacture, which will greatly limit the number of final stacks. . You may want to work closely with the manufacturer to define the number of cascades. Impedance control tools should be used to generate target impedance ranges for different layers. It is important to take into account the manufacturing tolerances provided by the manufacturer and the effects of adjacent wiring.
In the ideal case of signal integrity, all high-speed nodes should be routed in the inner layer of impedance control (such as stripline), but in fact, engineers must often use the outer layer for all or part of the high-speed node wiring. To optimize SI and keep the circuit board decoupled, the ground plane / power plane should be placed in pairs as much as possible. If there can only be one pair of ground / power planes, you will have only one general. If there is no power layer at all, you may encounter SI problems by definition. You may also encounter situations where it is difficult to simulate or simulate the performance of a circuit board before the return path of the signal is undefined.
4 Crosstalk and impedance control Coupling from adjacent signal lines will cause crosstalk and change the impedance of the signal lines. The coupling analysis of adjacent parallel signal lines may determine the "safe" or expected spacing (or parallel wiring length) between signal lines or between various signal lines. For example, if you want to limit the clock-to-data signal node crosstalk to within 100mV, but keep the signal traces parallel, you can find the minimum allowable spacing between signals on any given wiring layer through calculation or simulation. At the same time, if the design includes nodes with important impedance (either clock or dedicated high-speed memory architecture), you must place the wiring on one layer (or several layers) to get the desired impedance
5 Important high-speed node delay and time lag are the key factors that clock routing must consider. Because of the strict timing requirements, such nodes usually must use terminating devices to achieve the best SI quality. These nodes must be determined in advance, and the time required to adjust the placement and routing of components should be planned in order to adjust the pointers for signal integrity design.
6 Technology selection Different drive technologies are suitable for different tasks. Is the signal point-to-point or point-to-multi-tap? Does the signal come from the circuit board or stay on the same circuit board? What is the allowable time lag and noise margin? As a general criterion for signal integrity design, the slower the conversion speed, the better the signal integrity. There is no reason why the 50MHZ clock uses a 500PS rise time. A 2-3NS slew rate control device must be fast enough to ensure the quality of SI and help solve problems such as output synchronous switching (SSO) and electromagnetic compatibility (EMC).
In the new FPGA programmable technology or user-defined ASIC, you can find the superiority of the drive technology. With these custom (or semi-custom) devices, you have a lot of room to choose the driving amplitude and speed. In the early stage of design, it is necessary to meet the design time requirements of FPGA (or ASIC) and determine the appropriate output selection, including pin selection if possible.
At this design stage, appropriate simulation models must be obtained from IC suppliers. In order to effectively cover SI simulation, you will need an SI simulation program and corresponding simulation model (probably IBIS model).
Finally, during the pre-routing and routing phase, you should establish a series of design guidelines, which include: target layer impedance, wiring spacing, preferred device technology, important node topology and termination planning.
7 The pre-wiring stage The basic process of pre-wiring SI planning is to first define the input parameter range (driving amplitude, impedance, tracking speed) and possible topological range (minimum / maximum length, stub length, etc.), and then run every possible simulation combination , Analyze the timing and SI simulation results, and finally find the acceptable value range.
Next, the working range is interpreted as the wiring constraints of PCB wiring. Different software tools can be used to perform this type of "cleaning" preparation, and the routing program can automatically handle this type of routing constraints. For most users, the timing information is actually more important than the SI result. The result of the interconnect simulation can change the wiring, thereby adjusting the timing of the signal path.
In other applications, this process can be used to determine the layout of pins or devices that are incompatible with the system timing pointer. At this time, it is possible to completely determine the node that requires manual wiring or the node that does not require termination. For programmable devices and ASICs, the choice of output drive can also be adjusted at this time to improve SI design or avoid discrete termination devices.
8 SI simulation after routing Generally speaking, SI design guidelines are difficult to ensure that SI or timing problems do not occur after the actual routing is completed. Even if the design is conducted under the guidance of the guide, unless you can continue to automatically check the design, otherwise, there is no guarantee that the design fully complies with the guidelines, so problems will inevitably occur. The SI simulation check after wiring will allow planned design rules to be broken (or changed), but this is only necessary for cost considerations or strict wiring requirements.
9 The above measures can be used to ensure the SI design quality of the circuit board in the post-manufacturing stage. After the circuit board is assembled, it is still necessary to place the circuit board on the test platform and use an oscilloscope or TDR (time domain reflectometer) to measure the real circuit. Compare the expected results of the board and the simulation. These measurement data can help you improve the model and manufacturing parameters so that you can make better (less restrictive) decisions in the next pre-design survey.
10 Model Selection There are many articles about model selection, and engineers who perform static timing verification may have noticed that although all the data can be obtained from the device data sheet, it is still difficult to build a model. The SI simulation model is just the opposite, the model is easy to build, but the model data is difficult to obtain. In essence, the only reliable source of SI model data is IC suppliers, who must maintain a tacit cooperation with design engineers. The IBIS model standard provides a consistent data carrier, but the establishment of the IBIS model and its quality assurance are costly. IC suppliers still need to promote market demand for this investment, and circuit board manufacturers may be the only buyers. market
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