TI C6000 series DSP internal bus architecture, storage system and various peripherals (such as EDMA3 and PRU), especially on-chip program data RAM and Cache system, as well as peripheral EDMA controller, Video port, McBSP, McASP and SRIO interfaces.
On-chip bus bandwidth
C62x: two 32-bit load and storage buses;
C67x: Two 64-bit load, 32-bit memory bus;
C64x, C674x, C66x: two 64-bit load and storage buses;
Figure 1. On-chip bus width of the C6000
On-chip system block diagram of C6000 series DSP
Figure 2. On-chip system block diagram of the C6000 series DSP
Some devices contain L3 RAM at a lower speed
External memory: DDR2/3, SDRAM, asynchronous memory
MegaModule/CorePac module:
CPU
L1 RAMs/Cache
L2 RAMs/Cache
EDMA/EDMA2/EDMA3 controller, etc.
Switched Central Resource (SCR)/TeraNet for C66x devices
Central crossbar switch
Access from CPU and main peripheral devices such as EMAC, USB, PCIe to peripheral devices such as SPI, I2C, McBSP, etc.
C66x enhancements relative to C64x+
Only a unified bus instead of SCR
All memory processing is done to the EDMA controller;
Internal bus block diagram of the DM644x Davinci DaVinci processor
Internal bus block diagram of the DM644x Davinci DaVinci processor
Master device initiates data transmission
The slave device can only perform data transfer according to the command, but the slave device can initiate transmission by sending a transmission request interrupt to the CPU or EDMA3;
C64x on-chip storage
Figure 4. On-chip storage of the C64x
L1P Cache Controller
Direct Mapped (1 way)
The same frequency as the CPU, the size is 16KB, and each cache line size is 8 instructions, that is, 32 bytes.
L1D Cache Controller
2-way Cache
Same frequency as CPU, size 16KB, 64 bytes per cache line size
L2 RAMs, Cache Controller
C6414/15/16 = 1M Byte
C6411/DM642 = 256K Byte
The IDMA unit is added to the C64x+ for data transfer of the above three internal memories, and can also be stored from the on-chip to the config configuration register.
C6000 series DSP peripherals
Figure 5. Peripherals of the C6000 Series DSP
EDMA3 controller
DMA to complete memory or memory to peripherals, peripheral to memory data transfer, can be synchronized by external device events, can handle up to 64 events. Both DSP and ARM can access DMA channel resources, and for IDMAs added from C64x+, only DSP can access their channel resources.
In addition, there is QDMA channel (Quick DMA), which can perform DMA transfer between memories. It must be asynchronous processing, that is, it must be initiated by the CPU. There are 4-8 QDMA channels on the general DSP.
Some resources are shared between these DMA channels, including 128-256 parameter sets (PARAMs), as well as 64 Transfer Complete Flags (TCCS) and 2-4 Transfer Suspended Queues.
Master peripheral
VPSS (and other master devices)
USB, ATA, Ethernet, VLYNQ will share access to SCR;
PRU (Programmable RealTIme Unit) controller
Figure 6. PRU block diagram
The PRU includes two independent real-time RISC cores (approximately 40 instructions for logic, arithmetic, and flow control, etc.), software programming to implement peripherals, access to GPIO pins, PRUs and their own interrupt controllers, and The SCR accesses the memory while still performing power management control, such as turning off the ARM or DSP, and shutting down the processor or evoking the processor as much as possible based on system events.
Pin multiplexing, that is, programming to define the pins, to achieve the peripherals you need.
Multi-channel buffer serial port McBSP (MulTI-Channel Buffered Serial Port)
2/3 full-function synchronous serial ports;
The highest rate can reach 100Mbps
Support SPI bus protocol
Support for processing multiple channels (T1, E1, MVIP, ...)
Multi-channel audio serial port McASP (MulTI-Channel Audio Serial Port)
Supports up to 8 stereos (16 channels)
I2C support
Separate SPI or I2C device;
SRIO (Serial Rapid IO)
High-speed serial transmission, such as C6455 equipment supports 4 SRIO interfaces, which can perform chain connection communication; the data transmission speed of each interface reaches 3.25Gbps (enough to support one-way 1080P HD video), and can be associated with SRIO switch, hub And FPGA connection for high-speed data transmission.
Clock and Counter Timer / Counter
32-bit timer/counters can be used to generate interrupts;
64-bit timer/counters can be used to evaluate the algorithm;
Ethernet EMAC
10/100 Ethernet MAC, PIN and PCI multiplexing;
TCP/IP stack stack NDK provided by TI
Some newer devices support 10/100/1000 Ethernet MAC
Video Ports (DM Series Davinci Processor)
For the collection and display of video images;
Two 8/10-bit BT656 or raw RGB modes;
20-bit Y/C mode for 16/20-bit raw mode or HD application
Support 8-bit line scaling and chroma resampling
This article mainly introduces the internal bus architecture, memory system and various peripherals (such as EDMA3 and PRU) of TI's C6000 series DSP, especially on-chip program and data RAM and Cache system, as well as peripheral EDMA controller, Video Port, McBSP, McASP and SRIO interfaces.
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