How to help the FPGA family chip realize the detailed analysis of the bandwidth increase through EMIB

Intel's "Embedded Multi-Chip Interconnect Bridging" (EMIB) technology is perhaps an interesting event in this year's chip design space. It allows Intel to connect different heterogeneous dice on the same substrate without being too crowded. Today, Intel disclosed some details on how to achieve bandwidth gains through EMIB's help with the new Stratix 10 MX FPGA (Field Programmable Logic Array) family of chips.

Based on the onboard second-generation high-bandwidth memory (HBM 2) and Intel CPU and Radeon GPUs that have not yet officially announced a marriage, Intel will use EMIB to mount Stratix 10 MX FPGA chips, up to four “porcelain stickers” available. Up to 512GB/s of bandwidth.

In addition to the HBM2 memory stack, Intel also uses EMIB to attach four FPGA signal transceivers, such as PCIe. In the white paper (PDF), Intel also mentioned the challenges of using FPGAs and DDR4 memory to extend the current system-level architecture.

Three-channel DDR4-3200 memory may be able to meet the 80 Gb/s bandwidth requirements of today's FPGAs, but scaling and layout challenges are almost impossible to overcome in today's dog architecture.

As the demand for FGPA processing grows in the future, it is impossible to install enough DDR I/O pins on a single substrate infinitely to meet its bandwidth requirements.

Even if it is possible to place enough I/O pins on the FGPA package, each additional memory requires a very consuming I/O buffer to drive them, resulting in bandwidth requirements that are more sensitive than performance per watt. Design constraints in markets such as data centers.

Finally, Intel pointed out that placing 10 sets of DDR4 DIMM slots on a single PCB can theoretically achieve 256GB/s throughput (something in the future for FPGAs), but it will take up a considerable amount of space. The density of the data center does not increase or decrease.

Many of the constraints mentioned above are also a major reason why AMD began developing HBM memory to meet its GPU bandwidth requirements. Compared to GDDR5 memory chips that occupy a large amount of PCB area, HBM not only occupies less space, but also requires less wiring and energy consumption.

Currently, manufacturers need to use an interposer between the GPU and HBM memory. This extra silicon chip is also very popular, which not only increases the complexity of the package, but also limits the shrinkage of the overall size of the chip.

Therefore, Intel's positioning of EMIB is 'overcoming the challenge of using DDR4 and FPGA to increase bandwidth'. Unlike the interposer that is paired with HBM memory on Fuji and Vega GPUs, EMIB makes Intel's Stratix 10 MX FPGAs less restrictive when it comes to incorporating HMB2 memory.

Intel said that the use of EMIB can also benefit those similar substrates, because the bridge is only a small piece, using micro-bumps instead of through-silicon vias (TSVs) to connect the core.

In addition, the company does not have to worry about manufacturing challenges or reduce TSV production because it can package EMIB-integrated chips using standard flip-chip technology.

Ultimately, all these peculiar technologies allow Stratix 10 MX FPGA chips to enjoy exponential memory bandwidth growth. It supports up to 64 sets of concurrent memory accesses compared to current FPGA solutions (4~6 groups of DDR channels).

In addition, the FPGA chip is built with Intel's HyperFlex architecture and can run at 1GHz. With subsequent optimizations, it enables greater performance and application acceleration flexibility.