A brief overview of synthesizers based on phase-locked loop frequency synthesizers

Frequency synthesizers are an important part of modern wireless communication devices and directly affect the performance of wireless communication devices. Frequency synthesis technology has evolved into today's Direct Digital Synthesis (DDS) technology through early direct synthesis (DS) and phase-locked synthesis (PLL). Direct digital synthesis technology has the advantages of high resolution, fast conversion speed, low phase noise, etc., and plays an increasingly important role in wireless communication. With the development of large-scale integrated circuits, many frequency synthesis integrated circuits have been developed using phase-locked loop frequency synthesis technology. The frequency synthesizer is the heart of the electronic system and is the key device for determining the performance of the electronic system. With the development of technologies such as communication, digital television, satellite positioning, aerospace, radar and electronic countermeasures, the frequency synthesizer is getting higher and higher. Requirements. Frequency synthesis technology is a technique that transforms one or more highly stable, high-accuracy standard frequencies to produce a large number of discrete frequencies with the same high stability and accuracy. Since the introduction of frequency synthesis theory in the 1930s, it has developed rapidly and gradually formed four current technologies: direct frequency synthesis technology, phase-locked frequency synthesis technology, direct digital frequency synthesis technology and hybrid frequency synthesis technology. .

This article focuses on how to design a phase-locked loop frequency synthesizer, and gives an overview of the frequency synthesizer. It mainly introduces the phase-locked loop, and also designs and debugs the phase-locked loop frequency synthesizer. Explain.

1 overall design

There are many ways to achieve frequency synthesis, which can be directly synthesized, phase-locked loop, and there are many ways to implement phase-locked loop, such as variable crystal oscillator, variable frequency division coefficient M, and can also be realized by single-chip microcomputer. and many more. Several schemes for frequency synthesis using phase-locked methods are listed below.

1.1 Scheme 1

Figure 1.1 Scheme 1 block diagram

As shown in Figure 2.1, a ÷N variable divider is added to the feedback loop between the output of the VCO and the input of the phase detector. The highly stable reference oscillator signal fR is divided by R times to obtain a reference pulse signal of frequency fr. At the same time, the output of the voltage controlled oscillator is divided by N times to obtain a pulse signal with a frequency of fd, and the two pulse signals are compared in frequency or phase at the phase frequency detector. When the loop is in the locked state, the output signal frequency is: fo=N*fd. As long as the frequency division ratio N is changed, it is possible to output fo of different frequencies, thereby achieving the purpose of synsing fo from fr. Its output frequency point interval is Δf=fr.

1.2 Scheme 2

Figure 1.2 Scheme 2 block diagram

As shown in Figure 2.2, the frequency of 20KHZ is first generated by the crystal oscillator, that is, fi is 20KHZ. When the button 1 is pressed, the frequency division ratio M is 1, and the value of N is preset by the MCU programming, and can be changed correspondingly by "N plus 1 key" and "N minus 1 key". Then, the I/O port output of the single chip microcomputer is used as the data input of the 1- to N frequency dividing circuit. After passing through the phase-locked loop CC4046, the output frequency can be from 20K to 200KHZ and the frequency interval is 20KHZ. After the values ​​of M and N are determined, the specific value of the generated frequency can be calculated by the formula f0=fi*N/M. After being programmed by software, it is displayed by the MCU output. Similarly, when the button 2 is pressed, the signal generated by the crystal oscillator has undergone a very frequent frequency, and M is 10. When button 3 is pressed, M is 100 and the rest remains unchanged. Three different frequency bands and frequency intervals are achieved by changing the value of M.

1.3 Scheme 3

As shown in Figure 2.3, the frequency of 20KHZ, 2KHZ and 200HZ is generated by three crystal oscillators respectively, then the frequency is switched on and off by three buttons, and the selected frequency is sent to the input terminal of the phase-locked loop as the reference frequency. This achieves the choice of frequency bands. Different frequency intervals are implemented by 1- to N frequency dividing circuits. The data preset of the 1-N frequency dividing circuit can be realized by a decimal reversible counter. The frequency output from the phase-locked loop is measured by the digital frequency meter and then displayed by the LED.

Figure 1.3 Scheme 3 block diagram

1.4 program comparison

The above three schemes are all phase-locked frequency synthesizers, which are essentially the same. There are only differences in implementation methods. In the first scheme, variable frequency division is used to achieve frequency synthesis. Scheme 2 uses a crystal oscillator to divide the frequency twice as the input signal of the phase-locked loop. Scheme 3 uses three crystal oscillators. As far as the whole scheme is concerned, the process is simple and clear, the ideas are clear, and the implementation is relatively simple. Scheme 2 uses a single-chip microcomputer to complete the data input and final frequency conversion of the N-divider circuit, and sends it to the LED for display. In the third scheme, the single-chip microcomputer is not used, and the decimal reversible counter is used to realize the data preset of the 1-N frequency dividing circuit. Finally, the frequency measurement circuit is used to display the generated frequency output. In comparison, the circuit of the first scheme is simpler and easier to implement. Scheme 3 is a direct frequency synthesizer. The direct analog frequency synthesizer is prone to generate excessive spurious components and the large amount of equipment is therefore bulky, expensive and inconvenient to integrate is its main drawback. The advantage is that the frequency agility is fast and the phase noise is low.

1.5 program selection

After comparing the three options from various aspects, I chose the first option. The reason is that the first solution is simpler and easier to implement than the other two solutions. Option 2 adds the MCU module, but once the MCU is used, the system coordination ability of the whole circuit is higher, and the program part is also very demanding, which is difficult to implement; the third method uses a direct frequency synthesizer, and the direct analog frequency synthesizer The device has the disadvantage of generating too much spurious component and the large amount of equipment, so it is bulky and expensive, so I finally chose the first scheme as the design of this design.

2 unit module design 2.1 frequency source

The frequency source circuit is shown in Figure 2.1.

Use 74LS04 series crystal oscillator circuit:

Figure 3.1 Frequency source circuit diagram

The main function of the feedback resistor Rf is to make the inverter of the 74LS04 chip operate in an amplified state when it is static, and the crystal and capacitor C form a positive feedback network. As long as the input or output voltage of the NOT1 gate or the NOT2 gate has a slight change, it is fed back to the positive feedback network composed of the crystal and the capacitor, and amplified to cause oscillation. Since the oscillation output voltage waveform of the NOT1 gate and the NOT2 gate is not very good, the square wave of the shape standard is output through the NOT3 gate. According to the non-gate voltage transmission characteristics of the 74LS04 chip, Rf takes a value of 100kOhm, C=100pF, and the nominal frequency of the crystal is 2.000MHz.

2.2 Divider 1. Two-way frequency

Connecting the Q non-terminal and D-side of the D flip-flop can form one of the most commonly used two-way circuits.

As shown below:

Figure 2.2 divide-by-two circuit

2. Variable mode multi-frequency

After the inverter output terminal C of the 74LS161 is inverted and connected to the preset terminal LD, the modulus value of the frequency divider can be controlled by the change of the carry signal. The preset end is directly connected to the four-digit dial switch. TTL chip pins are suspended at a high level, so it is as simple as possible, eliminating the pull-up resistor.

As shown below:

Figure 2.3 Variable mode multi-frequency circuit

2.3 loop filter

There are not many external components of the entire 4046 chip. The key part is the loop filter. Its performance can determine the performance of the entire phase-locked loop circuit.

The loop filter can be: 1. RC integration filter 2. Passive proportional integration filter 3. Active filter. From the requirements of this design, the passive proportional integral filter is relatively simple and appropriate. As shown below:

Figure 2.5 Loop Filter Circuit

The cutoff frequency formula of the loop filter:

Wc=1/[(R3+R4)C2]

The bandwidth of the loop filter is around 1 kHz, where R3 = 50K is adjustable, R4 = 1k, and C2 = 1 uf. Optimal phase lock performance can be achieved with R3 regulation.

2.4 chip introduction 1. Integrated phase-locked loop HC4046

The HC4046 chip is the heart of the design frequency synthesizer.

The monolithic integrated phase-locked loop HC4046 uses a CMOS circuit process featuring a wide supply voltage range (3 to 18 V), high input impedance (approximately 100 MΩ), and low dynamic power consumption. The maximum frequency is 1.2 MHz at the power supply voltage VDD=15 V, which is commonly used in the middle and low frequency bands. The HC4046 integrates a phase comparator I, a phase comparator II, a voltage controlled oscillator, and a linear amplifier, a source follower, a shaping circuit, and the like.

The phase comparator I adopts an exclusive OR gate structure, and requires an input signal duty cycle of 50% in use. When the high and low levels of the two input signals are different, the output signal is high, otherwise, the output signal is low. The capture capability of the phase comparator I is related to the filter, and a suitable filter can be selected to obtain a wider capture range.

Phase Comparator II is controlled by the rising edge of a signal. It does not require a high duty cycle on the input signal, allowing an input of an asymmetric waveform with a wide capture range. The output of the phase comparator II is related to the frequency of the two input signals. When the input signal of the 14-pin is lower than the frequency of the comparison signal of the 3-pin, the output is logic "0", and vice versa, the logic "1" is output. If the frequencies of the two signals are the same and the phases are different, when the phase of the input signal lags behind the comparison signal, the phase comparator II outputs a positive pulse, and when the phase leads, the output is a negative pulse. When the frequency and phase of the two input pulses are the same, the output of the phase comparator II is in a high impedance state.

The voltage controlled oscillator requires external resistors R1, R2 and capacitor C1. R1, C1 are charge and discharge elements, and resistor R2 acts as a frequency compensation. The oscillation frequency of the VCO is not only related to the values ​​of R1, R2, and C1, but also related to the power supply voltage. The higher the power supply voltage, the higher the oscillation frequency.

Figure 3.6 shows the internal and peripheral circuit diagram and pin diagram of the HC4046. Among them, the 1-pin phase output terminal is high when the loop is locked, and is low when the loop is lost. The output of the 2-pin phase comparator I. 3 pin comparison signal input. 4-pin voltage controlled oscillator output. The 5 pin disable terminal is disabled when the high level is high. The low voltage allows the voltage controlled oscillator to work. 6, 7 feet external oscillation capacitor. 8, the negative and positive ends of the 16-pin power supply. The control terminal of the 9-pin voltage controlled oscillator. 10-pin demodulation output for FM demodulation. 11, 12 feet external oscillating resistor. The output of the 13-pin phase comparator II. 14-pin signal input. 15 pin internal independent Zener regulator tube negative.

Figure 2.6 Internal and peripheral circuit diagram and pin diagram of HC4046

2. Integrated inverter 74LS04

The 74LS04 chip is six independent inverters (6 non-gates). The power supply voltage is 5V, and the voltage range is 4.75~5.25V. The number of gates is 6, the input and output of each gate are TTL level ("0.8V low level" 2v high level), low level output current -0.4mA, high level output current 8mA. Each channel has a certain delay from the input phase to the output (9~15ns). Its pin diagram is as follows:

Figure 2.7 74LS04 pin diagram

3. Integrated trigger 74LS74

The 74LS74 chip is a dual D integrated flip-flop that is a rising edge triggered edge trigger. Table 3.9 is its function table. It uses a sustain blocking structure and is a rising edge triggered edge trigger that triggers a flip on the rising edge of the CP pulse ("0→1"). The secondary state of the flip-flop depends on the rise of the CP pulse to the state of the previous D, ie Qn+1 = D. Since the circuit has a blocking effect, the state change at the D terminal does not affect the state of the flip-flop output during CP=1. They are directly set to "0" and set to "1". When it is not necessary to directly set "0" and set "1", Should be set high.

Its pin diagram is as follows:

Figure 2.8 74LS74 pin diagram

Its function table is as follows:

Figure 2.9 74LS74 function table

4. Synchronous counter 74LS161

The 74LS161 is a four-bit binary synchronous counter that synchronizes the number of parallel presets, asynchronously clears, has four functions of clear, set, count, and hold, and has a carry signal output that can be used in tandem. Its pin diagram and logic function table are shown in Figure 3.10 and Table 3.11, respectively.

Figure 2.10 74LS161 pin diagram

EPETCP function

0&TImes;&TImes;&TImes;&TImes;clear

10××↑ preset number

1111↑ count

110×× keep

11 × 0 × keep QCC = 0

Table 2.11 74LS161 Function Table

2.5 basic composition of phase-locked loop

Many electronic devices need to work normally, usually requiring an external input signal to be synchronized with the internal oscillating signal. This can be achieved by using a phase-locked loop.

The phase-locked loop is a feedback control circuit, referred to as a phase-locked loop (PLL).

The phase-locked loop is characterized by the use of an externally input reference signal to control the frequency and phase of the internal oscillating signal of the loop.

Since the phase-locked loop can automatically track the input signal frequency to the input signal frequency, the phase-locked loop is usually used for the closed-loop tracking circuit. During the operation of the phase-locked loop, when the frequency of the output signal is equal to the frequency of the input signal, the output voltage maintains a fixed phase difference with the input voltage, that is, the phase of the output voltage and the input voltage is locked, which is the phase lock. The origin of the ring name.

The phase-locked loop is usually composed of phase detector (PD, Phase Detector), loop filter (LF, Loop Filter) and voltage controlled oscillator (VCO, Voltage Controlled Oscillator). The block diagram of the phase-locked loop is shown below. Shown.

SHAPE \* MERGEFORMAT

Figure 212 Block diagram of the phase-locked loop

The phase detector in the phase-locked loop is also called phase comparator, and its function is to detect the phase difference between the input signal and the output signal, and convert the detected phase difference signal into a uD(t) voltage signal output. After the low pass filter is filtered, the control voltage uC(t) of the voltage controlled oscillator is formed, and the frequency of the oscillator output signal is controlled.

Phase detector

The phase detector (PD) is a phase comparison device for detecting the output signal With input signal Phase difference between And put Converted to voltage Output, Called error voltage, usually For constant flow or a low frequency AC.

The phase detector is a very important component in the phase-locked loop, so some technical requirements are required for the phase detector. The main technical indicators are: (1) phase-detection characteristic shape; (2) phase-detection gain Kd; (3) leakage of input signal; (4) operating frequency and input and output impedance; (5) ability to discriminate between frequencies.

The circuit forms that make up the phase detector are many, with the following classifications:

(1) Diode balanced phase detector

(2) XOR gate detector

(3) Voltage switching type frequency discrimination phase detector

(4) Analog multiplier phase detector

2. Loop filter

LF is a low-pass filter circuit whose function is to filter out the nonlinearity due to PD. The useless combination of frequency components and interference generated in the generation produces a reflection only Size control signal . In addition to the role of low-pass filtering, it can also correct the function of the loop by reasonably selecting the parameters of each component. It is a very important malicious device for the capture, stabilization, noise filtering, loop bandwidth, etc. of the loop.

According to the feedback control principle, if the frequency of the VCO changes for some reason so that it is not equal to the input frequency, this will definitely make versus Phase difference , change, the phase difference is converted into error voltage by PD , the error voltage is obtained by LF filtering ,by To change the oscillation frequency of the VCO so as to approach the frequency of the input signal, and finally reach the same. The state in which the loop reaches the last state is called the locked state, of course, because the control signal is proportional to the phase difference, that is,

So in the locked state, It is impossible to be 0, in other words, it is locked. versus There is still a phase difference.

3. Voltage controlled oscillator

The VCO is the control object of the control system. The controlled parameter is usually its oscillation frequency. The control signal is the voltage applied to the VCO. Therefore, it is called a voltage controlled oscillator, that is, a voltage-to-frequency converter. In fact, there is another Current-frequency converter, but is still customarily called a voltage-controlled oscillator. Any type of oscillator, such as an LC oscillator, an RC oscillator, a multivibrator, etc., can constitute a voltage controlled oscillator. The voltage control frequency characteristics are shown in Figure 3.13.

Figure 2.13 VCO Voltage Control Frequency Characteristics

The slope of the curve is called the voltage control sensitivity or the frequency modulation sensitivity. The unit is rad/s·v. VCO instantaneous angular frequency versus The relationship is: = +

The instantaneous phase of the VCO is: = t +

Where: the inherent phase of the VCO is:

The VCO additional phase is: =

The above formula shows the output of the VCO Is the input The integral form, or VCO, is an integral part.

4. How the phase-locked loop works

The phase detector in the phase loop is usually composed of an analog multiplier, and the phase detector circuit composed of the analog multiplier is shown in Figure 3.14.

Figure 2.14 Phase detector circuit

The working principle of the phase detector is: set the signal voltage input by the outside world and the signal voltage output by the voltage controlled oscillator are:

The ω0 in the equation is the oscillation angular frequency of the voltage controlled oscillator when the input control voltage is zero or DC voltage, and is called the natural oscillation angular frequency of the circuit. Then the output voltage uD of the analog multiplier is:

The sum frequency component in the above equation is filtered out by the low pass filter LF, and the remaining difference frequency component is used as the input control voltage uC(t) of the voltage controlled oscillator. That is, uC(t) is:

The ωi in the equation is the instantaneous oscillation angular frequency of the input signal, and θi(t) and θO(t) are the instantaneous phases of the input signal and the output signal, respectively. According to the phasor relationship, the relationship between the instantaneous frequency and the instantaneous phase is:

which is

Then, the instantaneous phase difference θd is:

To differentiate between the two sides, the derivative of the frequency difference is:

The above equation is equal to zero, indicating that the phase-locked loop enters the phase locked state. At this time, the frequency and phase of the output and input signals remain constant, and uc(t) is a constant value. When the above formula is not equal to zero, it indicates that the phase of the phase-locked loop is not locked, the frequency of the input signal and the output signal are not equal, and uc(t) changes with time.

Due to the voltage control characteristics of the voltage controlled oscillator, this characteristic indicates that the oscillation frequency ωu of the voltage controlled oscillator is centered on ω0 and varies with the change of the input signal voltage uc(t). The expression for this attribute is:

The above formula shows that when uc(t) changes with time, the oscillation frequency ωu of the voltage-controlled oscillator also changes with time. The phase-locked loop enters the “frequency pull” and automatically tracks the frequency of the input signal to make the phase-locked loop enter. Locked state and keep the state of ω0=ωi unchanged.

3 overall circuit debugging

Use the simulation software to connect the circuit according to the schematic diagram, connect the power supply to the circuit board, and then observe the oscilloscope output for debugging.

3.1 VCO and frequency source part debugging

First check the circuit, adjust the output voltage of the DC regulated power supply before the wiring: 5V.

Because the VCO is generated by the PLL frequency synthesizer, most of the performance of the PLL is determined by it. Many performance parameters will be affected if the VCO fails to function properly. The VCO should be tested at the beginning of the commissioning phase to ensure that it provides a predetermined frequency range, gain, and output level. If you just want to test the VCO, you need to correct the PLL to cancel the closed loop control. A common method of "breaking" the loop is to open R3 and apply a laboratory power supply across C4, which allows the VCO tuning voltage to vary within the desired range. When the tuning voltage changes, the operating frequency of the VCO should be monitored on a frequency counter (or spectrum analyzer). Record the VCO operating frequency for a number of tuning voltage settings.

The frequency source is composed of a quartz crystal multivibrator. By adjusting the variable capacitor, the inverter inside the 74LS04 operates in the amplification region to start the circuit. At this time, the voltage across the crystal oscillator is tested to 2.5. V (because the power supply voltage is 5V) means that the frequency source is working properly.

3.2 Divider debugging

PLL designs tend to ignore the specifications of the digital divider. The operating conditions of the divider are generally good, but the PLL sometimes fails to achieve the expected performance due to the inability to maintain this good operating condition. All dividers have specifications for maximum input frequency (FMAX) and minimum input levels. In a design that ignores the FMAX specification, the divider will “lost pulses”. The closed loop will then detect that the frequency of the VCO is too low and the tuning voltage is further raised. The divider will lose more pulses and the loop will attempt to boost the VCO to a higher frequency. The loop will enter a "locked" state where the VCO tuning voltage is held at the positive supply voltage. Here, the problem that is easy to misunderstand at work is that the feedback divider must not only divide the expected output of the VCO, but must also correctly divide the highest frequency that the VCO is likely to generate under locking and unlocking conditions. . In order for the loop to operate reliably, the transient conditions encountered during startup or channel change must not cause feedback polarity reversal.

3.3 Overall circuit board debugging

This is based on the debugging of the phase locked loop. After the variable frequency divider is debugged, it is connected to the entire circuit. At this time, to lock the phase-locked loop, it is necessary to adjust the varistor to adjust the bandwidth of the loop filter to solve the loss of lock phenomenon. If the circuit principle and parameter settings are not wrong, then the oscilloscope is connected to the output to observe the output waveform. When the output square wave is adjustable and stable at 1.000MHz between 1.000MHz and 10.000MHz, the frequency is synthesized. The device works fine.

3.4 debugging results and reasons analysis

(1) After debugging, the waveform is sine wave:

In theory, the square wave generated by the crystal oscillator, then the final output should also be a square wave. After re-commissioning, it is the reason of the 74LS161 chip. The frequency is too high, so that the 74LS161 can't work normally. Finally, the original 74LS161 chip is used. Switched to the HC74LS161 chip, and then debugged, and surely the square wave output.

(2) When it is necessary to change the frequency, that is, from 1M to 10M, the dialer is dialed as required, but the frequency of the output waveform is not as stable as theoretically, but will jump. The reason is that the dialer is not working properly. The reason why the dialer does not work properly is that no pull-up resistor is connected. After connecting the pull-up resistor, the dialer is really easy to use. Of course, the waveform is not perfect. After all, the frequency synthesizer is very simple to make, it is not too complicated, and the parameters of the components also have an effect.

4 software introduction

The drawing software used in this design is Protel 99. Protel 99 is a very suitable drawing software. The following is a brief introduction to Protel 99.

Protel 99 adopts a new management method, that is, the management of the database. Protel 99 is the first full-scale printed board design system based on unique design management and teamwork technology in the desktop environment. All Protel99 design files are stored in a unique integrated design database and displayed in a unique integrated design editing window.

Protel 99 software follows the easy-to-learn feature of Protel's previous version. The internal interface is roughly the same as Protel 98, and some new functional modules have been added. Protel introduces the advanced technology of INCASES, Germany, and integrates signal integrity tools, accurate model and board analysis in Protel99 to help you achieve one-time success and eliminate blindness by using signal integrity analysis during the design cycle. The easy-to-use feature of Protel99 is the new "What's This" help. Press the small question mark in the upper right corner of any dialog box and select the information you want. Now you can quickly see the features of the feature, then use it in the design, press the button at the end of the status bar to help the consultant with natural language.

All Protel99 design files are stored in a unique integrated design database and displayed in a unique integrated design editing window. The interface to the design in Protel99 is called Design Manager. Using the Design Manager, you can manage edits to design files, set access to design groups, and monitor access to design files.

Organizing Design Files In the past, it took a few days to organize and manage 40 or more schematic, PCB, Gerber, Drill, BOM, and DRC files, and Protel99 stored all of the design files in a unique design database.

Organizing the files created by the hierarchical folder in the design database. The personal security system design database on the right has a folder called Design File. This folder is the main design file (schematic and PCB), and there are many sub-files. Folders, including PCB assembly files, reports, and simulation analysis. There is no limit to the depth of the hierarchy in which folders are created in the design database.

The design database has no restrictions on storing Protel design files. You can enter any type of design file into the database, such as reports written in MS Word, expense lists prepared in MS Excel, and mechanical drawings made in AutoCAD. Simply double-click the file icon in the design database, open the file in the appropriate editor, and the updated file is automatically saved to the design database. MS Word and Excel files can be edited directly in the Design Manager.

It is very easy to manage design files with Protel99's design manager in a comprehensive design database. The Design Manager works just like the MS Windows file manager, which can be used to navigate and organize files in the design database. Use Design Manager to create hierarchical folders in the design database and use standard file manipulation commands to organize the design files within these folders.

The heart of the design manager is the navigation panel on the left. The tree structure displayed on the panel is a familiar Protel software feature. In Protel99, this tree not only shows the logical relationship between the files of a schematic scheme, it also shows the physical structure of the files in the design database. The folder that is active in the navigation tree is the PCB assembly folder. Like the Windows File Manager, the Design Manager displays the contents of this folder on the right.

The difference between Design Manager and Windows File Manager is that the files that are already open are also displayed on the right.

To open a file, simply click on the file name you want to edit in the navigation tree or double-click the icon in the right folder.

The individual files opened in the design database are displayed in the same design editing window with cards, making it very easy to know where the current work is, especially in large designs. To view different files together, you can split the design edit window into multiple regions.

5 summary

This course design is designed as a phase-locked frequency synthesizer. The most critical part of it should be the phase-locked loop part. The most critical technology is of course the phase-locking technology, the most critical loop filter in the phase-locked loop. Through the design of this course, the basic principle of the phase-locked loop frequency synthesizer is mastered. The working characteristics of the integrated phase-locked loop chip HC4046 are analyzed, and a lot of knowledge is obtained from an application example of the integrated phase-locked loop chip HC4046. The implementation process is: the crystal oscillator generates a fixed frequency 2M, divided by 2 as an input signal of the phase-locked loop 1MHZ, and the 74LS161 realizes 1 to 10 frequency division as another input signal. The phase-locked loop has a lock time of less than 2 ms during operation. The output is 150MHz-175MHz and the frequency interval is 5kHz. Among them, the frequency division of 1 to 10 is obtained by the counter 74LS161. When changing, you can dial the dialer to reach the desired frequency.

Data Acquisition Digital Potentiometers

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