In the past two years, interface standards for eliminating data transmission bottlenecks between ICs, boards, and systems have emerged in an endless stream. This article will analyze some of the most popular standards for standard components of communication applications and examine the reasons for many new standards. In addition, it explores how designers can solve the problem of interoperability.
Optoelectronic device connected to a serial-parallel converterIn high-speed fiber-optic communication systems, the transmitted data stream requires format conversion, that is, a serial format at the time of optical fiber transmission and a parallel format during electronic processing. Serializer-deserializers (generally referred to as serial-parallel converters) are used to implement this conversion. The interface between the serial-to-parallel converter and the photosensor is typically a high-speed serial data stream that utilizes a coding scheme to implement different signaling so that the embedded clock can be recovered from the data. The serial stream is available at 1.25Gb/s (Gigabit Ethernet), 2.488Gb/s (OC-48/STM-16), 9.953Gb/s (OC-192/STM-64) according to supported communication standards. ) or 10.3Gb/s (10 Gigabit Ethernet) transmission.
Serial to parallel converter to framer interfaceIn the world of Sonet/SDH, data transmission in optical fibers is often in the form of frames. Each frame includes additional information (for synchronization, error monitoring, protection switching, etc.) and payload data. The transmitting device must add additional information to the frame in the output data, and the receiving device must extract the payload data from the frame and use the additional information of the frame for system management. These operations are done in the framer.
Since the framer needs to implement some complex digital logic, it determines the interface technology used between the serial-parallel converter and the framer, and uses a highly integrated IC fabricated in a standard CMOS process. Current CMOS processes cannot support 10Gb/s serial data streams, so parallel interfaces between serial-to-parallel converters and framers are required. The most popular choice at the moment is SFI-4, developed by OpTIcal Internetworking Forum, which uses two 16-bit parallel data streams (one in each direction) at speeds up to 622 Mb/s. SFI-4 uses the same source synchronous clock as many new interfaces, that is, the clock signal and the data signal are transmitted together by the transmission device. The source synchronous clock can significantly reduce the offset between the clock signal and the data signal, but it does not completely eliminate the offset effect caused by mismatching the PCB line length. The 16 data signals and clock signals all use IEEE-1593.6 standard LVDS signaling. The interface only needs to transfer data back and forth between the serial-parallel converter and the framer, and the distance is short, so there is no need for complicated flow control or error detection.
A similar interface exists in Ethernet. Between the Physical Coding Sublayer (PCS) and Physical Media Connection (PMA) layers of a 10 Gigabit Ethernet PHY, the IEEE-802.3ae specification provides an interface called XSBI. This 10 Gigabit 16-bit interface has 16-bit parallel data streams and source-synchronous clocks in each direction. Both data and clock use IEEE-1593.6 standard LVDS signaling. The data channel uses a 64b/66b encoding scheme with a clock frequency of 644MHz.
The 10 Gigabit Ethernet specification uses a serial interface to connect the MAC (Media Access Control) layer to the PHY (physical) layer. This interface, called XAUI, is also known as the 10 Gigabit Connection Unit interface, which is a four-channel serial interface that transmits 2.5 Gb/s payload data per channel, 8b/10b encoding for each The bit rate of the channel is as high as 3.125 Gb/s. This interface is typically used to connect a MAC to a separate module containing PHY and optical components. Xenpak optical modules developed according to several manufacturers' multi-source protocols use the XAUI interface. It will be mentioned later that XAUI is also used for the system backplane.
Interface between framer and network processor and other componentsThe data transmitted between the framer and the network processor can represent many different data streams. The additional data contained in the Sonet/SDH frame indicates the location of each data stream in the data payload, which needs to be transmitted between the framer and the network processor and associated devices, such as the classification engine and traffic manager. In addition, network processors and related devices implement complex tasks such as scheduling of packets to the switching chip, managing packet content to ensure that no illegal data enters the network, and measuring bandwidth for specific applications or users to have priority. . Due to the complexity of these tasks, a flow control scheme needs to be implemented between the framer and the network processor.
Commonly used interfaces between framers, network processors, and related devices include Utopia interfaces, POS-PHY interfaces, SPI interfaces, and Flexbus interfaces. Each interface is suffixed with levelX and its level indicates the nominal data rate. Level 2 means that the data rate in each direction is 622 Mb/s, Level 3 is 2.488 Gb/s, Level 4 is 9.953 Gb/s, and Level 5 is 39.8 Gb/s. Therefore, the nominal bandwidth of POS-PHYLevel4 is 9.953 Gb/s. The Utopia interface is designed for data streams containing fixed length ATM cells.
The POS-PHY interface (the package on the Sonet physical layer) was developed by PMC-Sierra and Saturn. Many features are identical to the Utopia interface. One improvement is worth noting, that is, POS-PHY can meet the needs of different length packets, while Utopia only Suitable for fixed unit lengths. This indicates that the POS-PHY interface is designed for applications that transmit IP packets of varying length directly on the Sonet/SDH transport layer without the need for an ATM layer, and is therefore referred to as a packet on Sonet.
Developed by AMCC, the Flexbus interface handles variable-length IP packets on the Sonet transport layer. AMCC's FlexbusLevel4 has been adopted by the Optical Networking Forum as SPILevel4Phase1 (commonly abbreviated as SPI-4.1) and has been released as an industry standard specification. The specification provides a 64-bit parallel point-to-point data path in each direction. It uses HSTLclass1I/O, has a source synchronous clock frequency of 200MHz, and provides a quarter rate interface and a 16-bit parallel data channel.
POS-PHYLevel4 has also been adopted by the Optical Networking Forum and is named SPILevel4Phase2 (usually abbreviated as SPI-4.2). The interface has a 16-bit parallel data channel using IEEE-1593.6 standard LVDS, and the source synchronous double data rate clock frequency is at least 311 MHz. Many applications of SPI-4.2 use a more frequent clock because the interface transmits packet tags and routing information in addition to the data payload. Therefore, designers often use SPI-4.2, each with a data rate of up to 840 Mb/s and a cumulative bandwidth of 13.4 Gb/s in each direction.
Although SPI-4.2 was developed for data packets on Sonet, it has been adopted by other applications in the communications industry. As a flexible interface that supports multiple data streams and has flow control in each data stream, it can be used as an effective interface for 10 Gigabit Ethernet and also for storage area networks (SANs). There are a variety of new products on the market that use the SPI-4.2 interface, and some products are under development, in addition to the Sonet/SDH framer and network processor, including the TCP Offload Engine (TOE) and 10 Gigabit Ethernet. MAC.
Interface between network processor and switch fabricThere are two types of interfaces between the network processor and related devices and switch fabrics: one is an interface that does not need to transmit data on the backplane, and the other is an interface that needs to transmit data on the backplane.
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