This article introduces an embedded system simulation method, which connects the software debugger software Keil uVision2 and the hardware language simulator software Modelsim through a specially designed instruction set simulator ISS to realize the synchronous simulation of software and hardware.
Explanation of acronyms:
BFM: Bus function module. In HDL hardware language simulation, BFM completes the conversion between abstract description data and specific timing signals.
PLI: Verilog programming language interface, is the interface definition for data exchange between C language module and Verilog language module.
TCL: Literally means tool command language, which is an interpreted execution language. Popular EDA software generally integrates TCL. Using TCL, users can write scripts that control EDA tools to automate tool operations.
ISS: CPU instruction set simulator, which can execute the machine code of the CPU.
TFTP: Simple File Transfer Protocol, Windows tftp.exe is the client implementation of this protocol.
SMART MEDIA: A memory card commonly used in digital cameras and MP3.
DMA: Direct memory access. Used for high-speed data transfer between external devices.
MAC: Media Access Controller. This article refers to the network card chip.
Preface
In traditional embedded systems, the design cycle, hardware and software development are carried out separately, and the system is integrated after the hardware is completed. In many cases, real-time software and overall debugging are started after the hardware is completed. Co-simulation of software and hardware is a technology that can start debugging the program as soon as possible before the physical prototype is available.
Co-simulation of software and hardware makes it possible for software design engineers to start debugging in the early stages of design, while using traditional methods, design engineers cannot perform debugging until the hardware design is completed. Some software can complete the coding of tasks without hardware support, such as algorithms that do not involve hardware. The code that interacts with the hardware is written before the hardware is obtained, but only after running on the hardware can the code be debugged. Through the use of software and hardware co-simulation technology, this design debugging process can be started early in the design. Since software development is usually completed in the latter part of the system development, starting debugging earlier in the design cycle may make this project complete earlier, and this technology will reduce accidents when the hardware and software are connected for the first time. Risks caused by delayed completion.
Before the physical prototype is obtained, the software and hardware co-simulation technology is used to verify the interface between the hardware and the software, so that you will not spend too much time on the later system debugging. When you do get the physical prototype and start running the software on it, you will find that the tested software part will work normally, which will save a lot of time and effort later in the project.
The software and hardware co-simulation system consists of a hardware execution environment and a software execution environment. Usually the software environment and the hardware environment have their own debugging and control interfaces. The software interacts with the hardware through a series of bus cycles initiated by the processor. This article introduces a software and hardware co-simulation system based on the development of a Mini Web card.
The core of the program is to use a 51 single-chip simulation engine GoldBull ISS51 (hereinafter referred to as ISS51). ISS51 is a plug-in of the 51 single-chip development environment Keil uVision2. ISS51 has an interface to connect Keil and the hardware simulation environment Modelsim, which can realize software and hardware synchronous simulation. In this system, Keil is used as the software debugging interface, Modelsim is used as the hardware simulation and debugging interface, ISS51 is responsible for software execution, monitoring software breakpoints, single-step execution, memory and register data return to Keil, CPU bus timing generation and capture, internal functions Module (such as timer, serial port) operation and other functions.
Introduction to Mini Web Card
Mini Web card is a Web server running on a single-chip microcomputer, which provides network port connection, has a large-capacity file system, and provides TFTP and HTTP services. Although the software system is more complicated, after optimized compilation, the execution code is still less than 25K, leaving enough room for subsequent upgrades.
51CPU adopts SST89 series, this kind of CPU has ISP function, can download the target code directly to CPU through RS232 serial port.
DMA control logic is a programmable logic device, which uses ALTERA's CPLD EPM240. The main function is to realize DMA transfer between peripheral devices. Because 51CPU is very inefficient for IO access, it takes 24 clock cycles to perform an IO access, and transferring data between peripheral devices requires more clock cycles. Using DMA control logic can reach 3 clock cycles to transfer. One byte. This system deals with multiple network protocols, and requires a large number of messages to be sent and received and file system access. Using DMA can greatly improve the data processing speed of the 51 single-chip microcomputer. DMA channel mainly includes data block transfer between MAC chip and RAM, and data block transfer between SMART MEDIA and RAM.
The network card chip uses AX88796, the main advantage is that it can easily interface with 51CPU; supports 100M Ethernet, high speed; there is a large received message buffer, which can smooth network traffic and reduce the messages caused by the slow processing speed of 51CPU Discard and resend.
SMART MEDIA is a mobile memory card, mainly used to store files. Mini Web card supports 8M to 256M SMD cards.
The file system is a new development module of the Mini Web card. The test of the file system is mainly carried out through TFTP. For this reason, the TFTP service program on the Mini Web card is specially designed to support formatting SMART MEDIA, obtain the remaining space, and obtain the file name list , Upload, download and delete files.
The necessity of software and hardware co-simulation:
Mini Web card has many software modules, and the risk of software development is relatively high. Software has a strong dependence on hardware. The access drive of FLASH memory, network card drive, and DMA drive need to be coordinated and debugged by software and hardware.
The development of the file system is easier and faster in the simulation environment. For example, at the end of the simulation, you can switch the data in the SMART MEDIA simulation model to a disk file. At the beginning of the simulation, load the data in the disk file into the SMART MEDIA simulation model. When locating file system problems, this one The function is very useful.
The use of software and hardware co-simulation facilitates the early design of the system. The external RAM access efficiency of the 51 single-chip microcomputer is low, and the data block transfer between memory copy and external devices is a waste of time. Realizing a large amount of data copy operation or data block verification and comparison operations in the CPLD can greatly improve the 51 single-chip microcomputer's ability to process data. Through software and hardware co-simulation, the performance improvement of CPLD processing data can be evaluated.
Mini Web card software and hardware co-simulation system:
The main problem that the software and hardware co-simulation solves is the system function design and verification. It does not solve the problems of power supply, filter capacitor, and bus level compatibility.
To do system simulation, we must first model the hardware system. What we are concerned about is the correctness and enforceability of the system design.
The serial port in the system is only used to support ISP downloading software, and the software part does not do any operation on the serial port, so system simulation can be ignored.
For the network card chip AX88796, the manufacturer did not provide a simulation model. The interface between it and the CPU conforms to the ISA interface standard, and the software's operation of the AX88796 is designed according to the NE2000 standard network card chip, so we have established a simulation model of the network card chip. We designed a MAC BFM to simulate the ISA interface of the network card chip. The NE2000-defined register is implemented in the C model. The MAC BFM and the NE2000 register C model exchange data through PLI.
The SRAM simulation model is very easy to obtain. Many device manufacturers provide Verilog simulation models, but the Verilog simulation models provided by the device manufacturers contain complex delay control codes, which will affect the simulation speed. Based on experience, we can ensure that SRAM is correctly applied in single-board design without timing problems, so we can use a simplified SRAM simulation model, which is our own design, and the effective code is only a dozen lines.
51CPU BFM is responsible for the generation and capture of single-chip pin timing. 51CPU BFM is tightly bundled with ISS51 and is provided by the ISS51 installer.
SMART MEDIA is a simulation model provided by Samsung, and we also use the same type of memory card from Samsung. This model can be used to verify the correctness of the software operation SMART MEDIA and the interface timing of the DMA Controller.
DMA Controller is a part of Mini Web card hardware development. It applies logic design code to simulation, which can not only check the correctness of logic design, but also make the entire simulation system run normally.
Virtual network card
To do system simulation, it is necessary to input stimuli from the real world and transfer the output of the simulation system to the real world. Even if it cannot be connected to the real world, it should provide input that simulates the real world, and detect and analyze the output of the simulation system.
For the Mini Web Card, it is connected to the real environment through a network port. Using the virtual network card technology, the MAC C Model in Figure 3 can be communicated with the virtual network card.
For an application running on a Windows system, it does not know whether the network card is virtual or real. The application sends and receives data through the virtual network card, in fact it is communicating with the simulation system on the network.
In this way, you can use TFTP to transfer the web page file to the Mini Web card emulation system, and use IE to browse the web pages in the Mini Web card emulation system. All the functions of the Mini Web card can be tested.
Use the network sniffer Sniffer to monitor the message flow of the virtual network card, which is convenient for protocol debugging.
Simulation acceleration technology
Software and hardware co-simulation, the bottleneck affecting the simulation speed is the simulation of the HDL code part. If you do not try to improve the simulation speed of the HDL code part, software debugging is very inefficient.
One of the ways to improve the speed of hardware simulation is to use event synchronization in software and hardware simulation, and keep the software and hardware synchronized only when the CPU accesses IO.
The second method of simulation acceleration is hardware simulation system clock sleep. For the Mini Web card, only the DMA Controller is controlled by the clock. During the period when the software is not operating the DMA Controller, the operation of the DMA Controller is meaningless. Therefore, the clock can be put to sleep during non-DMA operation; During the second IO access, the time difference from the last IO access is given, and this time difference can be treated as the time period for the clock to sleep. If ISS51 continuously performs IO access, clock dormancy will not occur. DMA Controller works in query mode and can adopt clock sleep technology without causing inconsistency between simulation and real results.
The third method is to shorten some long-delay time parameters in the SMART MEDIA simulation model. Because while waiting for SMART MEDIA to enter the ready state, the CPU must continuously query IO, which affects the simulation speed. We are mainly used for software function verification, and this modification is also acceptable.
The fourth method is to use external interrupts carefully in software design, because once the interrupt is started, ISS51 needs to check whether there is an interrupt signal in each machine cycle, which causes software simulation and hardware simulation to synchronize on each instruction, which affects the simulation speed. . If you must use an external interrupt, it is recommended to use the C model instead of the Verilog model, so that the simulation speed will not be affected; or the user can use the ISS51 control command to enable the ISS51 interrupt module at the appropriate time according to the timing of the external interrupt generated by the external module.
On an ordinary PC (CPU is AMD Athlon 1000, SDRM512M 133), run the Mini Web card simulation system, and use the PING command to test the response speed of the Mini Web card simulation system:
Reply from 10.10.112.76: bytes=32 time=64ms TTL=128
Using IE to open the web page file in the Mini Web card emulation system, it feels that there is not much difference in the speed of dial-up Internet access. Create multiple TFTP connections, transfer or download web files to the simulation system at the same time, and use IE to browse the web at the same time, but no response interruption occurs.
to sum up
Using software and hardware co-simulation, the Mini Web card can simulate all functions without hardware, which enhances the confidence in the success of the system design. Co-simulation of software and hardware facilitates system design adjustments, can estimate performance in the early stages of design, and facilitates software and hardware debugging. It is a technology worth popularizing.
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