A design scheme of high-speed real-time data acquisition system

0 Preface

Currently, USB has been widely used in data acquisition systems. At present, the USB 2.0 specification is used more. As test and measurement requirements continue to increase, USB 2.0 has become increasingly difficult to meet. The new USB 3.0 specification addresses some of the limitations of USB 2.0 and is ideal for modern test and measurement systems.

1 USB 2.0 performance and limitations

Universal Serial Bus (USB) is a widely used system bus, which is widely used in the field of test and measurement. Currently the most widely used is the USB2.0 standard with a communication rate of up to 480Mbps. But at the same time, the USB2.0 standard also has the following shortcomings:

1) Half-duplex communication

USB2.0 uses half-duplex communication, and can only transmit data in one direction at a time. It is often difficult to meet the requirements in situations where bidirectional high-speed data transmission is required.

2) Need host scheduling

The USB2.0 standard adopts the master-slave structure in the transmission scheduling. The computer needs to initiate the IN Token or OUT Token first, and the USB device can perform data transmission. After a data transmission is completed, the next token must be waited for, which greatly restricts the real-time data transmission. Sex.

3) Communication rate is not high compared to competitors

USB competitors include 1394 and eSATA. The newer 1394b standard data transfer speed reaches 800Mbps, almost double the USB2.0 HS. And eSATA data transfer speed is higher.

2 USB 3.0 SS (SuperSpeed) Standard Introduction

To enhance the performance and competitiveness of USB, the USB Alliance has introduced a new USB 3.0SS (SuperSpeed) standard. The standard uses two differential links for full-duplex communication at speeds up to 5.0Gps, which is not only higher than the 1394b standard, but also competitive with eSATA.

USB 3.0 adds 2 pairs of differential links to 2.0, specifically for transmitting SS differential signals. The mechanical characteristics of the host-side interface are compatible with USB 2.0, while the device side uses a new interface form to accommodate the addition of two pairs of differential signal lines. The Type B connector of the USB2.0 interface can be plugged into the USB 3.0 device, and the device works in USB 2.0 mode; however, the USB 3.0 Type B connector cannot be plugged into the USB 2.0 device.

In addition, USB 3.0's bus power supply capacity is 1A, making it suitable for power-hungry devices such as mobile hard drives without the need for an external power supply.

3 CYUSB3014 chip introduction

The CYUSB3014 is a USB 3.0 controller from Cypress, the leader in the USB industry. The controller integrates a 200MHz ARM9 controller, 512K bytes of RAM and a USB 3.0 physical layer with a programmable 100MHz GPIF II interface.

Figure 1 is a logical block diagram of the chip. The chip can be used in many fields such as digital cameras, data acquisition, test and measurement equipment.

CYUSB3014 chip logic block diagram

4 system hardware design

In this system, a piece of AD6644 is used for data conversion. This is a 14-bit high speed ADC from AnalogDevice with a maximum sampling rate of 40Msps.

The functional block diagram of the entire system is shown in Figure 2.

Functional block diagram of the system

In the figure, the sensor converts the external signal into an electrical signal; the amplification and filtering part amplifies and filters the weak electrical signal output by the sensor to remove external interference; the AD6644 collects and converts the amplified and filtered signal under the control of the FPGA; The FPGA reads the AD output and writes the data to the FIFO inside the chip according to the GPIF II interface specification of the CYUSB3014. In addition, the FPGA can also adjust the amplification filter circuit parameters according to the current signal characteristics to obtain a better signal-to-noise ratio.

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