Secondary systems of intelligent substations usually include electronic transformers, merging units, switches, and protection and measurement equipment. These devices must operate on a uniform time base, which places stringent requirements on the clock synchronization system of the intelligent substation. How is the intelligent substation microsecond timing system implemented?
Time is the basic physical quantity, then time will have the problem of precision, and different time sources have different precision. If the Apple Watch is used with the iPhone, the error with the UTC time does not exceed 50ms. The 50ms error is negligible for human perception, but it is unsatisfactory if used in a smart substation.
Secondary systems of intelligent substations usually include electronic transformers, merging units, switches, and protection and measurement equipment. These devices must operate on a uniform time base to meet event sequence record (SOE), fault recording, real-time data acquisition time consistency requirements, ensure line fault location, phasor and angle of attack dynamic monitoring, crew and grid The accuracy of the parameter verification. These requirements impose stringent requirements on the clock synchronization system of the intelligent substation.
The IEC61850 standard divides the substation into a station space layer, a bay level and a process layer. The requirements for time synchronization accuracy are different for each layer of equipment. The interval layer device needs to reach the ms precision; while the process layer device needs to achieve the synchronization precision of μs due to the main transmission sample value and the trip information. The intelligent substation test equipment DT6000 series (DT6000, DT6000E and DT6000S) has a timing accuracy of up to μs, which fully meets the timing accuracy of the equipment in each layer of the substation.
DT6000 series timing system
Figure 1.1 Timing of the DT6000 Series
The timing of the DT6000 series supports IRIG-B, PPS and IEEE1588, as shown in Figure 1.1. All three protocols are hard-decoded by FPGA. After decoding, they are converted to UTC time-scale. The time is given to other protocols such as SMV and GOOSE. For example, the time stamps of SMV and GOOSE are hard time stamps, and the time stamp is used by FPGA to time. Information is inserted into the message, and the message information and time are saved in real time. At the same time, the FPGA also performs the calibration, which corrects the error (μs level) caused by the local crystal oscillator, and dynamically adjusts the uniform adjustment error value.
1.1.1 Right timePPS time
There are two important criteria for determining the normality of PPS:
(1) The time interval between rising edges of adjacent pulses is 1 s. When the interval between the rising edges of adjacent pulses differs from the ideal interval time (1s) by more than 10 μs, the input is judged to be abnormal.
(2) The pulse width is greater than 10μs and the interval is greater than 500ms. The input is considered abnormal when the measured pulse width is less than 10 μs, or the measured pulse interval is less than 500 ms.
The DT6000 series filters the input signal according to the above two discriminating factors to remove the glitch signal. As shown in Figure 1.2, after the DT6000E passes the PPS pair, the SMV sample counter is cleared in the whole second.
Figure 1.2 The whole second SMV sample counter is cleared
2. IRIG-B timing
The frame period of the IRIG-B code is 1 s, including 100 symbols, and each symbol period is 10 ms, that is, the symbol rate of the IRIG-B code is 100 pps. The IRIG-B code has three symbols, binary "0", "1" and position identification flag Px, and the pulse widths are 2ms, 5ms and 8ms, respectively. The pulse signal is shown in Figure 1.3.
Figure 1.3 IRIG-B symbol map
Two consecutive "P" symbols represent the beginning of the whole second, and the pulse front of the second "P" symbol is the "punctual" reference point, defined as "Pr", which carries the current time and time control related information. . IRIG-B's full-second "punctual" reference point, SMV's sampling counter needs to be cleared, which is the same as PPS, as shown in Figure 1.2.
Figure 1 shows the IRIG-B timing of the DT6000E.
Figure 1.4 IRIG-B timing
3. IEEE1588 timing
The decoding and timing of IEEE1588 messages are performed in the FPGA and work in the Slave mode. The time stamp is the process of marking the synchronization message with the local clock information when the synchronization message enters or leaves the protocol stack. The acquisition of the timestamp directly affects the accuracy of the clock synchronization. The location of the timestamp is close to the physical layer. The better the avoidance of the delay jitter of the packet in the protocol stack, the higher the synchronization accuracy can be achieved. . In the FPGA, the message decoding and time stamping are time stamping on the MII layer, and the hardware is time stamped with the highest precision.
Figure 1 shows the IEEE 1588 timing of the DT6000E.
Figure 1.5 IEEE 1588 timing
1.1.2 School hoursThe DT6000 series will correct the local crystal oscillator error value while timing. Figure 1.6 is an example of the adjustment of the calibration time. It can be seen from the figure that the first coarse adjustment value is +99, and the second precision adjustment is positive. At this time, Value=+99+9=+108. The third precision adjustment is reversed. At this time, Value=+108-2=+106, the counter is also uniformly adjusted while the Value value is being acquired.
Figure 1.6 Schematic diagram of the school time
The timing circuit (FPGA) works at 100MHz main frequency. After the actual measurement, after the calibration is stable, the accuracy error does not exceed 20 cycles (10ns) in the environment where the temperature changes little. After the calibration, the timing accuracy is from The μs level can be changed to 200 ns. And after using the calibration circuit, the high accuracy of the local time can be maintained for a long time after the time-of-day device is removed.
1.1.3 timingThe DT6000 series supports IRIG-B code and PPS timing. The DT6000S has two optical serial ports, so it supports two optical serial ports for simultaneous timing. As shown in Figure 1.7, the IRIG-B code timing interface of the DT6000E is equivalent to the timing of the PPS.
Figure 1.7 IRIG-B code timing
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