Wafer-level packaging to large-size chips

Wafer-level packaging (WLP) technology is steadily applied to small chip applications. For large-size chip applications such as DRAM and flash memory, the prospects for mass production are not yet clear, but the ideal WLP has high reliability and can operate at high frequencies, which is expected to change the current situation in which such large-size chips cannot be applied. WLP generally has good power integration features, supports wafer-level testing, can adapt to chip feature size reduction, and reduce costs.

The latest advances in WLP technology can satisfy every requirement of the so-called ideal WLP. It has been demonstrated that a flexible layer can increase reliability. Two metal layers on WLP increase power and signal integrity. Unpackaged substrates minimize the trace length of high-speed applications. Copper pillars are added on top of the flexible layer for direct wafer-level testing and burn-in. WLP using reconstituted wafers can solve the problem of chip size reduction and can reduce packaging costs by using lamination instead of spin coating and minimizing lithography steps. This article discusses these technologies and highlights the technological advancements needed to advance mass production applications of WLP.

For small chip devices with a small number of I/Os, WLP technology is a less expensive packaging solution than chip-scale package (CSP) technology. This is because the package substrate is eliminated, the packaging process is highly parallelized and manual operation is minimized. WLP technology also provides the smallest possible form factor, so WLP has found its way into small logic and analog ICs, RF ICs, image sensors, and MEMS packaging. The adoption of 1WLP is still limited to chip applications with small area and small amount of I/O, such as memory, DRAM, SRAM, and digital signal processors (DSPs).

For chip applications with a small but large area of ​​DRAM and other I/Os, WLP technology still presents significant challenges, including thermal fatigue reliability, cost, shrinking chip area, and wafer-level testing. To further promote the use of WLP for large-size chips, the packaging industry needs to develop high-reliability, high-quality electrical performance (including good signal and power integrity for high-frequency applications), wafer-level testing, and feature size reduction Solutions and low-cost WLP solutions. In recent years, these areas have made progress.

Thermal fatigue reliability

Because the coefficient of thermal expansion (CTE) between the chip and the PCB is clearly mismatched, thermal fatigue reliability is a significant concern for WLPs with chip sizes greater than 5×5 mm. Some people have conducted comprehensive studies on various factors that affect the reliability of thermal fatigue at the plate level. 2 After research, compared with other parameters, larger bump spacing, large bumps, and large solder spacing have a significant impact on improving thermal fatigue reliability. DRAM uses a relatively large chip, with a small number of I/Os, and a standardized 0.8mm bump pitch. However, in spite of these favorable factors, due to the absence of a flexible layer, this chip cannot meet the required stability standards for most consumer products and commercial products.

A properly designed, flexible layer with optimized mechanical properties can significantly improve thermal fatigue reliability. Both simulated data and experimental data show that the correct choice of flexible material can determine the reasonable distribution of thermo-mechanical load between the weld and the metal trace. The protective layer above the flexible layer can increase the radius of the flexible bump at the edge and avoid stress concentration. The Young's modulus of the flexible material also has an impact on the reliability of the package. Simulations were performed using the three properties shown in Table 1, and Table 2 shows the effect of modulus on the stress in the solder and RDL traces (in GPa). In the first group, material A (Young's modulus of 0.16 GPa) was used as a buffer layer, protective layer, and solder resist paint, resulting in less stress on solder and RDL traces. Using material C (Young's modulus 3.0 GPa) as a solder resist paint, the stress on the solder was too great. Using material B (Young's modulus of 2.4 GPa) as a flexible buffer layer resulted in greater stress in the RDL traces. Gardner et al. also demonstrated the importance of the protective layer. 3Gardner's research shows that the performance of flexible WLP with sharp bump edges is worse than that of a control sample without a flexible layer because the failure mode is fatigued from the solder joint to the metal trace cracks at the edges of the flexible bumps. It was found that the spiral trace design can greatly improve the reliability of the trace. 4 Stress concentration has a particularly significant effect on the intersection of metal lines above the boundary between hard and flexible materials.