The all-in-one inverter circuit is widely used, and the welding machine of many manufacturers at home and abroad adopts this main circuit structure. The advantage of the full bridge circuit is that the output power is large, and the power switch tube is required to have a low withstand voltage, which is convenient for selecting a tube. In the hard-switching overseas circuit, the IGBT is turned on under high voltage, turned off at high current, and is in the process of forcing switching. Whether the power device IGBT can be used normally and reliably plays a vital role.
The function of the driving circuit is to power-amplify the PWM signal outputted by the control circuit to meet the requirements of driving the IGBT. Its performance is directly related to the switching speed and power consumption of the IGBT, the efficiency and reliability of the whole machine. As the switching frequency increases, the optimal design of the drive circuit is more important.
2. Analysis of working process of hard-switching full-bridge circuitThe main circuit of the full-bridge inverter consists of main components such as power switch IGBT and intermediate frequency transformer. As shown in Figure 1, the fast recovery diodes VD1~VD4 are connected in parallel with lGBT1~IGBT4 in reverse, and the reverse current generated by the load is applied to protect the IGBT. . IGBT1 and IGBT4 are a group, IGBT2 and IGBT3 are a group, each group of IGBTs is turned on and off at the same time. When the excitation pulse signal drives IGBT1, IGBT4 and IGBT2, IGBT3 in turn, the inverter main circuit converts DC high voltage to 20 kHz. The AC voltage is sent to the intermediate frequency transformer and output by the step-down rectification filter.
Figure 1 Full-bridge inverter circuit
One of the major drawbacks of full-bridge inverters is the problem of biasing the IF transformer. Under normal operating conditions, the power switching device has the same conduction pulse width in the first half of the working period and the second half of the working cycle, and the saturation pressure drop is equal, and the front and rear half cycles alternately. There is no remanence in the transformer core. However, if the output width of the IGBT drive circuit is asymmetrical or other causes, a positive and negative half-cycle imbalance will occur. At this time, the magnetic core in the transformer will accumulate residual magnetism in a certain half-cycle, and a "unidirectional bias" phenomenon occurs. With a few pulses, the unidirectional flux of the transformer can be saturated, the transformer loses its function, and it is equivalent to a short circuit. This is extremely dangerous for IGBTs and can cause an explosion.
Another disadvantage of bridge circuits is that they are prone to shoot-through. The straight-through phenomenon means that the IGBTs of the same bridge overlap in the conduction period of the front and rear half cycles, and the main circuit board, the huge applied current instantaneously passes through the IGBT.
In view of the above two shortcomings, from the perspective of driving, the designed driving circuit must satisfy the four-way driving waveform completely symmetrical, strictly limit the maximum working pulse width, and ensure that the dead time is sufficient.
3. Dynamic analysis of IGBT switching processThe IGBT is a composite device of a MOSFET and a bipolar transistor, and its driving is similar to that of a MOSFET driving, and is a voltage control device with a small driving power. However, there is an inter-junction capacitance between the gate and the emitter of the IGBT and between the gate and the collector. There is leakage inductance in its emitter loop. Due to the influence of these distributed parameters, the driving waveform and ideality of the IGBT are ideal. The drive waveform produces large variations and creates factors that are detrimental to IGBT turn-on and turn-off.
The equivalent circuit of the IGBT switch is shown in Figure 2a. E is the driving signal source, R is the negative in the driving circuit, Rg is the gate series resistance Cge, Cgc is the parasitic capacitance between the gate and the emitter, the collector, and Le is the emitter loop leakage inductance, using the inductor L1 Parallel to the diode VD as a load.
Figure 2 IGBT turn-on waveform
The IGBT turn-on waveform is shown in Figure 2b. At time T0, the IGBT is in the off state, the gate drive voltage begins to rise, and the rising slope of Uge is determined by Rg and Cgc, and rises faster. To t1. Uge reaches the gate threshold (about 4~5V), and the collector current begins to rise. There are two main factors that cause the Uge waveform to deviate from the original trajectory: one is the negative feedback effect of the distributed inductance Le in the emitter circuit; the other is the Miller effect of the gate-collector capacitance Cgc. At time t2, Ic reaches the maximum value, the collector voltage Uce drops, and Cgc discharges, the drive circuit current increases, so that the partial pressure on Rg and R increases, which also causes Uge to drop. Until time t3, Uce drops to 0, Ic reaches the steady state value, and Uge reaches the maximum value with a faster rate of increase.
The IGBT turn-off waveform is shown in Figure 2c. At the time T0, the gate drive voltage begins to drop. At the time t1, the water reaches the Ic. The lGBT enters the linear working area, and Uce starts to rise, charging Cgc and Cge. Due to the coupling charging effect on the two parasitic capacitors, During t1~t2, Uge is basically unchanged. At time t3, Uce rises and Uge and Ic drop to zero with the inherent impedance between the gate and emitter.
It can be seen from the above analysis that the factors that have a great influence on the turn-on and turn-off process of the IGBT are the resistance, Le and Cge of the driving circuit. Therefore, when designing the driver circuit, the IGBT with smaller Cgc should be selected, and the process of turn-on and turn-off should be improved by reasonable wiring and selection of reasonable resistance.
4. Practical drive circuit design and experimental results of IGBTFor the full-bridge inverter with hard-switching trigger mode, the four-way drive circuit is identical, but the circuits must be isolated from each other on the circuit to prevent interference or false triggering. The four-way drive signals are divided into two groups according to the trigger phase. in contrast. Figure 3 shows a gate drive circuit. The rectifier bridges B1 and B2 and the electrolytic capacitors C1 and C2 form a rectification and filtering circuit to provide +25V and -15V DC drive voltages for the drive circuit. The function of the optocoupler 6N137 is to achieve isolation between the control circuit and the main circuit and to transmit the PWM signal. The resistor R1 and the Zener diode VS1 form a PWM sampling signal, and the resistor R2 limits the optocoupler input current. Resistors R3 and R4 and voltage regulators VS3 and VS4 form a 5.5V optocoupler level limiting circuit, respectively, which provide driving levels for the optocoupler and MOSFET Q3. Q3 operates under the optocoupler control state. The MOSFETs Q1 and Q2 form a push-pull amplifier circuit, and the amplified output signal is input to the IGBT gate to provide a gate drive signal. When the control signal is input, the optocoupler U is turned on, Q3 is turned off, and Q2 is turned on to output the +15V driving voltage. When the control signal is zero, the optocoupler U is turned off, Q3 and Q1 are turned on, and the output voltage is -15V. When the IGBT is turned off, the gate is provided with a negative bias to improve the anti-interference ability of the lGBT. The voltage regulators VS3 to VS6 respectively limit the input voltage of Q2 and Q1 to -10V and +15V, preventing Q1 and Q2 from entering deep saturation and affecting the response speed of the MOS tube. The resistors R6 and R7 and the capacitor C0 are Q1 and Q2 to form a bias network. The capacitor C0 is for accelerating the rising current of the drain current of the Q2 tube when it is turned on, providing an overshoot current to the gate, and accelerating the gate conduction.
Figure 3 principle of the gate drive circuit
The IGBT gate withstand voltage is generally around ±20V, so the gate is voltage-protected at the output of the driver circuit, the shunt resistor Rge and the reverse series limiting voltage regulator, as shown in Figure 4.
Figure 4 gate protection circuit
The gate series resistance Rg has a great influence on the IGBT turn-on process. Rg is small to speed up the turn-off speed and reduce the turn-off loss, but too small will cause di/dt to be too large, resulting in a large collector voltage spike. According to the specific requirements of this design, Rg selects 4.7Ω.
The parasitic inductance of the gate wiring and the parasitic capacitance between the gate and the emitter will generate an oscillating voltage, so the gate lead should be transmitted by twisted pair and driven as short as possible, preferably no more than 0.5 m. Reduce the wiring inductance.
The wiring of the four-way driver circuit optocoupler and PWM two output signals is shown in Figure 5.
Figure 5 Wiring of the two-way output signal of the four-channel driver circuit optocoupler and PWM
The experimental waveform is shown in Figure 6. Figure 6a is a gate driven four output waveform. When measuring the four-way drive waveform at the same time, it should be detected without turning on the main circuit. Because the multi-track oscilloscope is used to detect, only one probe's ground terminal is connected to the reference potential to prevent a short circuit from burning the oscilloscope. The ground reference can be used to select the common reference potential only when detecting circuit signals that are isolated from each other. Figure 6b is the ensemble-emitter voltage Uce waveform of the IGBT. Since the circuit signals of the IGBTs in the full-bridge inverter circuit are non-isolated, the multi-track oscilloscope cannot be performed with a common probe. The voltage waveform is measured by a high-voltage isolation probe, and the oscilloscope reading is 1/50 of the actual value. As can be seen from the waveform, lGBT works normally. In the bridge inverter circuit affecting the Uce waveform, in addition to the influence of the drive, there are many other factors, not to elaborate here. It can be seen from the experimental results that the driving circuit can make the main circuit work safely.
Figure 6 Experimental result waveform
5 ConclusionFor the full-bridge inverter circuit, the drive circuit of the IGBT module is designed with discrete components. The four-way drive waveforms are strictly consistent, phase accurate, and the leading edge of the gate signal is steep. The experimental results show that the developed driver circuit fully meets the driving requirements of IGBT, and can make IGBT work reliably, which has certain practical value.
Igbt inverter buffering law: 1 IntroductionThe snubber circuit, also known as the snubber circuit, is an integral part of high power converter technology.
The main function of the snubber circuit is to control the shutdown surge voltage of the power devices such as IGBTs and the freewheeling diode to restore the surge voltage and reduce the switching loss. Make full use of the power limit of the IGBT.
It should be pointed out that the snubber circuit can reduce the switching loss of the power device because the switching loss is transferred from the device itself to the buffer. The purpose is to reduce the power consumption of the power device and ensure safe operation, but the total switching loss comes. cut back.
2 IGBT buffer circuit features and typesThe characteristics of the IGBT snubber circuit and the traditional GTR snubber circuit are different. The main performances are as follows: 1 IGBT has a large safe working area, and the snubber circuit does not need to protect against the secondary breakdown of the associated Darlington GTR. State voltage. 2 In general applications, the operating frequency of the IGBT is much higher than the operating frequency of the Darlington GTR. In each switching process, the snubber circuit must be discharged through the IGBT or itself, resulting in a large total switching loss.
The main factors that should be considered when designing an IGBT snubber circuit are: the layout structure of the power circuit, the power level, the operating frequency, and the cost.
Figure 1 shows three general-purpose IGBT snubber circuits. The buffer circuit shown in Figure la consists of a non-inductive capacitor and is between Cl and E2 of the IGBT module. This snubber circuit is suitable for low power levels and is very effective and low cost for suppressing transient voltages. As the power level increases, this snubber circuit may oscillate with the DC bus parasitic inductance. This can be avoided by the snubber circuit diagram lb, which clamps the transient voltage to suppress resonance. The RC time constant τ of such a snubber circuit should be set to about 1/3 of the circuit switching period, that is, τ ≈ T / 3 = 1 / (3 Å). However, in the case where the power level is further increased, the loop parasitic inductance of the lb type snubber circuit becomes so large that the transient voltage cannot be effectively controlled. The high current circuit can adopt the buffer circuit diagram lc. The buffer circuit can effectively suppress the oscillation and also has the advantage of less parasitic inductance of the loop, and the disadvantage is high cost. In the ultra-high power circuit, in order to reduce the stress of the diode in the snubber circuit, a method in which the la and c-type snubber circuits are simultaneously used can be adopted.
Figure 1 General IGBT snubber circuit Figure 2 shows the typical shutdown voltage waveform of the lc type snubber circuit. The peak of the starting voltage (ΔV1) in the figure is caused by the combination of the parasitic inductance of the snubber circuit and the positive recovery of the snubber diode. If the snubber diode uses a fast recovery diode matched to the IGBT, the voltage spike depends mainly on the snubber inductance Ls. In this case, ΔV1 can be estimated as
△V1=Ls·di/dt (1)
Ls in the formula - the equivalent parasitic inductance of the snubber circuit
Di/dt——di/dt of turn-off instant or diode recovery instant
In a typical IGBT power circuit, the di/dt in the worst case is close to 0.02 Ic/ns. If the limit of ΔV1 has been determined, the di/dt value can be used to estimate that the maximum current allowed by the snubber circuit is 400A, and ΔV1 is limited to 100V, and the worst case di/dt is approximately
Di/dt=0.02&TImes;400=8A/ns
Solved by (1): Ls=△V1/di/dt=100÷8=12.5nH
From the above calculations, we can know that the high-power IGBT circuit must have a very low inductance buffer circuit, otherwise the transient voltage will not be well suppressed.
Figure 2 Typical shutdown voltage waveform using a buffered mushroom
When designing the snubber circuit, the parasitic inductance of the snubber diode and the snubber capacitor leads should be considered. The use of small diodes and small capacitors in parallel is less than the equivalent parasitic inductance of a single diode and a single capacitor, and try to use low or no sense capacitors. In addition, the design of the snubber circuit should be connected as close as possible to the lGBT module. The above measures help to reduce the parasitic inductance of the snubber circuit.
After the initial surge voltage is turned off as shown in Figure 2, the transient voltage rises again as the snubber capacitor is charged, and the second rising peak voltage ΔV2 is a function of the snubber capacitance and the DC bus parasitic inductance. The law of conservation of energy can be used to determine ΔV2.
Lp in the formula - bus parasitic inductance
I——working current
C——buffer capacitor value
△V2——buffer voltage peak
If the limit value of ΔV2 has been determined, the value of the snubber capacitor can be determined for equation (2) for a given power circuit.
In the actual power circuit design, the following measures can be taken to reduce the required capacitance: 1 using a flat-type bus bar, the positive and negative poles are overlapped, separated by a spacer plate to obtain the minimum busbar parasitic inductance; 2 because C The value is proportional to the square of the shutdown current, so take the necessary current limiting technique to limit the maximum current of the power circuit; 3 because the C value is inversely proportional to the square of ΔV2, if there is a certain amount between ΔV2 and VCES of the IGBT. The margin allows the snubber capacitor value to be significantly reduced.
Table 1 gives a set of recommended design values ​​for the snubber circuit, where the main bus inductance is the target value set in the table, and di/dt = 0.02 Ic / ns is set, and the overshoot voltage ΔV1 = 100V. Taking this set of values ​​as a reference can provide convenience for the design of the buffer circuit.
The design of the snubber circuit is directly related to whether the power circuit such as the inverter can work normally and safely. Experiments show that a properly designed buffer circuit can not only effectively reduce the switching stress, but also suppress high-frequency oscillation, and it can itch low switching loss and improve the operating frequency. In practical applications, it is best to design the snubber circuit on a printed circuit board and install it on the busbar on the IGBT module for best results.
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